#!/usr/bin/perl

#******************************************************************
#
# sv_mod_dir.pl module
#
#******************************************************************
#
# UC Davis Confidential Copyright © 2009 ECE Department
#
#******************************************************************
#
# created on:	04/25/2009 
# created by:	jwwebb
# last edit on:	$DateTime: $ 
# last edit by:	$Author: $
# revision:	$Revision: $
# comments:	Generated
# 
#******************************************************************
# Revision List:
#
#		1.0	04/25/2009	Initial release
# 
#******************************************************************
# SystemVerilog Module Directory Template
#	
#  This utility is intended to make creating new SystemVerilog modules easier.
#  
#  This script will create a new directory called <mod_name>
#  when you type the following command:
#
#  	sv_mod_dir.pl -m <mod_name>
#
#  Below is the usage for this script:
#  
#  	Usage: sv_mod_dir.pl [-h] [-v] [-m <MODULE>] [-t]
#  	
#  	        -h              Print Help.
#  	        -v              Verbose: Print Debug Information.
#  	        -m <MODULE>     SystemVerilog HDL Module Name.
#  	
#  	        Example:
#  	                sv_mod_dir.pl -v -m trig_mux -a
#  			
#  The script will generate the empty SystemVerilog HDL directory template 
#  described below:
#
#        <module_name>/
#                doc/    Put module related documentation here.
#                sim/    Top level simulations directory.
#                        rtl_sim/ RTL Simulations (behavioral)
#                                archive/ RTL simulation archives
#                                bin/ RTL simulation scripts
#                                bench/ Test Bench Source
#                                run/ For running RTL simulations.
#                                src/ Special sources for RTL simulations.
#                                out/ Trace dump and other useful output from RTL simulation
#                                log/ Log files
#                syn/    Synthesis directory.
#                        bin/ For synthesis scripts
#                        run/ For running synthesis scripts
#                        src/ Special sources for synthesis
#                        out/ For generated netlists (Synplicity rev_1, verilog)
#                        log/ Log files (including reports)
#                sw/     Software directory.
#                        matlab/ For Matlab scripts
#                        perl/ For Perl scripts
#
#******************************************************************

#******************************************************************
# CPAN Modules
#******************************************************************
use strict;
use Getopt::Std;

#******************************************************************
# Custom Modules
#******************************************************************
use SystemVerilogTools qw( genTBTestFile
     		           genSVLowModule
		         );

#******************************************************************
# Constants and Variables:
#******************************************************************
my (%opts)=();
my ($module);
my ($debug);
my (%svH, $sv_rH);

#******************************************************************
# Retrieve command line argument
#******************************************************************
getopts('hvm:',\%opts);

my $optslen = scalar( keys %opts );
print("Number of Options on Command-Line: $optslen\n") if $opts{v};
#check for valid combination command-line arguments
if ( $opts{h} || !$opts{m} || ($optslen eq "0") ) {
    print_usage();
    exit;
}

# parse command-line arguments
$module = $opts{m};
$debug = $opts{v};

#******************************************************************
# Make Date int MM/DD/YYYY
#******************************************************************
my $year      = 0;
my $month     = 0;
my $day       = 0;
($day, $month, $year) = (localtime)[3,4,5];

#******************************************************************
# Grab username from PC:
#******************************************************************
my $author= "$^O user";
if ($^O =~ /mswin/i) { 
    $author= $ENV{USERNAME} if defined $ENV{USERNAME};
} else { 
    $author = getlogin();
}

#******************************************************************
# Initialize Verilog Hash:
#******************************************************************
$svH{ 'username' } = $author;
$svH{ 'day' } = $day;
$svH{ 'month' } = $month;
$svH{ 'year' } = $year;
$svH{ 'module' } = $module;
$svH{ 'debug' } = $debug;

#******************************************************************
# Check to see if SystemVerilog Module Already Exists:
#******************************************************************
die "Oops! A directory called '$module' already exists.\n" if -e $module;

#******************************************************************
# Generate SystemVerilog Module Filenames:
#******************************************************************
$sv_rH = genFileNames(\%svH);

#******************************************************************
# Generate Lower SystemVerilog Module:
#******************************************************************
if ($opts{m}) {
    print("Module: $opts{m}\n") if $debug;
    $sv_rH = genModuleDir($sv_rH);
}

exit;
 
#******************************************************************
# Generic Error and Exit routine 
#******************************************************************
 
sub dienice {
	my($errmsg) = @_;
	print"$errmsg\n";
	exit;
}

sub print_usage {
	my ($usage);
	$usage  = "\nUsage: $0 [-h] [-v] [-m <MODULE>]\n";
        $usage .= "\n";
        $usage .= "\t-h\t\tPrint Help.\n";
        $usage .= "\t-v\t\tVerbose: Print Debug Information.\n";
        $usage .= "\t-m <MODULE>\tSystemVerilog HDL Module name.\n";
        $usage .= "\n";
        $usage .= "\tExample:\n";
        $usage .= "\t\t$0 -v -m trig_mux \n";
        $usage .= "\n";
	print($usage);
        return;
}

sub genFileNames {
    ##########################################################################
    # Generate SystemVerilog Filenames:
    #
    #  The sub-routine genFileNames() will create the module filenames.
    #
    #  Usage: $sv_rH = genFileNames(\%svH);
    #
    ##########################################################################
    my ($sv_rH) = shift;	# Read in user's variable.
    my (%svH) = %{ $sv_rH };	# De-reference hash.

    my ($module) = $svH{ 'module' };	# Module Name.
    my ($debug) = $svH{'debug'};	# Print out Debug Info.


    # Create sub-module name:
    my $mfile = $module;
    $mfile .= ".sv";

    # Create sub-module test bench name:
    my $tbfile = "test_";
    $tbfile .= $module;
    $tbfile .= ".sv";

    my $tclfile = $module;
    $tclfile .= ".tcl";

    my $rfile = "$module/";
    $rfile .= "ReadMe.txt";


    # Stuff names into Hash for use elsewhere:
    $svH{ 'file' } = $mfile;
    $svH{ 'moduleFile' } = $mfile;
    $svH{ 'testBFile' } = $tbfile;
    $svH{ 'tclFile' } = $tclfile;
    $svH{ 'readmeFile' } = $rfile;
    
    ##########################################################################
    #
    # Return data to user
    #
    ##########################################################################
    return \%svH;
}

sub genModuleDir {
    ##########################################################################
    # Generate Lower-Level SystemVerilog Module:
    #
    #  The sub-routine genModuleDir() will create the module directory and 
    #  all of the necessary sub-directories.
    #
    #  Usage: $sv_rH = genModuleDir(\%svH);
    #
    ##########################################################################
    my ($sv_rH) = shift;	# Read in user's variable.
    my (%svH) = %{ $sv_rH };	# De-reference hash.

    my ($module)  = $svH{ 'module' };	# Module Name.
    my ($mfile)   = $svH{ 'moduleFile' };
    my ($tbfile)  = $svH{ 'testBFile' };
    my ($tclfile) = $svH{ 'tclFile' };
    my ($rfile)   = $svH{ 'readmeFile' };

    my ($debug) = $svH{'debug'};	# Print out Debug Info.

    # Create the directory structure.
    system("mkdir $module");
    system("mkdir $module/doc");
    system("mkdir $module/sim");
    system("mkdir $module/sim/rtl_sim");
    system("mkdir $module/sim/rtl_sim/archive");
    system("mkdir $module/sim/rtl_sim/bin");
    system("mkdir $module/sim/rtl_sim/bench");
    system("mkdir $module/sim/rtl_sim/run");
    system("mkdir $module/sim/rtl_sim/src");
    system("mkdir $module/sim/rtl_sim/out");
    system("mkdir $module/sim/rtl_sim/log");
    system("mkdir $module/syn");
    system("mkdir $module/syn/bin");
    system("mkdir $module/syn/run");
    system("mkdir $module/syn/src");
    system("mkdir $module/syn/out");
    system("mkdir $module/syn/log");
    system("mkdir $module/sw");
    system("mkdir $module/sw/matlab");
    system("mkdir $module/sw/perl");

    # Place the simulation files in the top-level src directory.
    $sv_rH = genSVLowModule(\%svH);
    system("rm -f $mfile.bak");
    $sv_rH = genTBTestFile(\%svH);
    system("cp -R ~/bin/digital_design/sim_bot/* $module/");
    system("rm -f $module/sim/rtl_sim/bench/test_sim_bot.sv");
    system("mv $mfile $module/");
    system("mv -f top.sv $module/sim/rtl_sim/bench/");
    system("mv -f $tbfile $module/sim/rtl_sim/bench/");
    system("perl -pi -e 's/bot/$module/g' $module/sim/rtl_sim/bench/*.sv");
    system("rm -f $module/sim/rtl_sim/bench/*.bak");

    # Place the synthesis files in the syn directory.
    system("mv $module/syn/bin/bot.tcl $module/syn/bin/$tclfile");
    system("perl -pi -e 's/bot/$module/g' $module/syn/bin/$tclfile");
    system("rm -f $module/syn/bin/$tclfile.bak");
    system("perl -pi -e 's/bot/$module/g' $module/syn/bin/Makefile");
    system("rm -f $module/syn/bin/Makefile.bak");
    system("perl -pi -e 's/bot/$module/g' $module/syn/bin/synhooks.tcl");
    system("rm -f $module/syn/bin/synhooks.tcl.bak");
   
    open (my $outF, ">", $rfile) or dienice("file open failed");

    my $readme =<<"EOF";
ReadMe File

This folder contains the SystemVerilog files for the $module design.

For more information on using these scripts see Jeremy Webb's website:

        http://www.ece.ucdavis.edu/~jwwebb/hdl_design.shtml

EOF

    printf($outF "$readme");

    ##########################################################################
    #
    # Return data to user
    #
    ##########################################################################
    return \%svH;
}