#!/usr/bin/perl

#******************************************************************
#
# ver_mod_low.pl module
#
#******************************************************************
#
# UC Davis Confidential Copyright © 2009 ECE Department
#
#******************************************************************
#
# created on:	05/02/2009 
# created by:	jwwebb
# last edit on:	$DateTime: $ 
# last edit by:	$Author: $
# revision:	$Revision: $
# comments:	Generated
# 
#******************************************************************
# Revision List:
#
#		1.0	05/02/2009	Initial release
# 
#******************************************************************
# Verilog HDL Tools Module
#
#  This utility is intended to make designing with Verilog HDL
#  simpler. This utility supports the following options:
#
#      Usage: vertools.pl [-h] [-v] [-z] [-f <FILE>]
#      
#              -h              Print this help message.
#              -v              Verbose: Print Debug Information.
#              -z              Generate new Verilog HDL low-level module file from Template.
#              -f <FILE>       Verilog HDL input file.
#      
#  Example of Module Instantiation:
#  
#	vertools.pl -z -f sample.v
#  
#  Save this file in your home 'bin' directory.
#
#******************************************************************

#******************************************************************
# CPAN Modules
#******************************************************************
use strict;
use warnings;
use Getopt::Std;

#******************************************************************
# Custom Modules
#******************************************************************
use VerilogTools qw( genVerLowModule );

#******************************************************************
# Constants and Variables:
#******************************************************************
my (%verH, $ver_rH);
my (%opts)=();
my ($file);
my ($debug);

#******************************************************************
# Retrieve command line argument
#******************************************************************
getopts('hvf:z',\%opts);

my $optslen = scalar( keys %opts );
print("Number of Options on Command-Line: $optslen\n") if $opts{v};
# check for valid combination of command-line arguments
if ( $opts{h} || !$opts{f} || !($opts{z}) || ($optslen eq "0") ) {
    print_usage();
    exit;
}

# parse command-line arguments
$file  = $opts{f};
$debug = $opts{v};

#******************************************************************
# Make Date int MM/DD/YYYY
#******************************************************************
my $year      = 0;
my $month     = 0;
my $day       = 0;
($day, $month, $year) = (localtime)[3,4,5];

#******************************************************************
# Grab username from PC:
#******************************************************************
my $author= "$^O user";
if ($^O =~ /mswin/i) { 
    $author= $ENV{USERNAME} if defined $ENV{USERNAME};
} else { 
    $author = getlogin();
}

#******************************************************************
# Initialize Verilog Hash:
#******************************************************************
$verH{ 'username' } = $author;
$verH{ 'file' } = $file;
$verH{ 'day' } = $day;
$verH{ 'month' } = $month;
$verH{ 'year' } = $year;
$verH{ 'debug' } = $debug;

#******************************************************************
# Generate Lower Verilog HDL Module:
#******************************************************************
if ($opts{z}) {
    print("Filename: $opts{f}\n") if $debug;
    $ver_rH = genVerLowModule(\%verH);
}

exit;
 
#******************************************************************
# Generic Error and Exit routine 
#******************************************************************
 
sub dienice {
    my($errmsg) = @_;
    print"$errmsg\n";
    exit;
}

sub print_usage {
    my ($usage);
    $usage = "\nUsage: $0 [-h] [-v] [-z] [-f <FILE>]\n";
    $usage .= "\n";
    $usage .= "\t-h\t\tPrint this help message.\n";
    $usage .= "\t-v\t\tVerbose: Print Debug Information.\n";
    $usage .= "\t-z\t\tGenerate new Verilog HDL low-level module file from Template.\n";
    $usage .= "\t-f <FILE>\tVerilog HDL input file.\n";
    $usage .= "\n";
    $usage .= "\tExample of Module Instantiation:\n";
    $usage .= "\t\t$0 -z -f sample.v \n";
    $usage .= "\n";
    print($usage);
    return;
}