Using Perl in your SystemVerilog HDL Design Flow

Today is: Tuesday January 06, 2009

How to use Perl in your SystemVerilog HDL Design Flow?

Anyone who designs with SystemVerilog HDL has probably grown tired of generating module instantiations in a hierarchical design, or creating a new top level or lower level SystemVerilog HDL module. I have generated a few Perl Scripts that will automatically generate the module instantiations, top level module, and lower level module for you. These Perl Scripts can be invoked from within VI/VIM/GVIM, or a DOS Command Window. If you invoke them from within VI, the script output will be printed in the current file. If you invoke them from within a DOS Command Window, then you will have to either cut and paste into your SystemVerilog HDL file or pipe the output to a new file. Below are the scripts:

sv_mod_top.pl : SystemVerilog HDL Top Level Module Template Perl Script [download]
sv_mod_low.pl : SystemVerilog HDL Lower Level Module Template Perl Script [download]
sv_inst.pl : SystemVerilog HDL Module Instantiation Perl Script [download]
sv_tb.pl : SystemVerilog HDL Test Bench Module Generation Perl Script [download]

How to use sv_mod_top.pl?

This utility is intended to make creating new SystemVerilog HDL modules easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate. This script will create a new text file called "new_module_name.sv" when you type the following command:

	!! sv_mod_top.pl new_module_name.sv

The script will generate the empty SystemVerilog HDL template for you in the file "new_module_name.sv". Note: "new_module_name.sv" is the name of the new SystemVerilog HDL file and can be anything you like. The module declaration uses Verilog 2001 ANSI-C style. You can either use VI or a DOS Command prompt to run this script. If you want to use a DOS Command prompt, then see the instructions below:

Change directory to the desired directory
- cd C:\design\new_module
- If the directory "new_module" does not exist type: mkdir C:\design\new_module, before changing directory.
Type the following: perl sv_mod_top.pl new_module_name.sv
When the script is finished you will see the message: "The script has finished successfully! You can now use new_module_name.sv."

How to use sv_mod_low.pl?

	!! sv_mod_low.pl new_module_name.sv

Change directory to the desired directory
- cd C:\design\new_module
- If the directory "new_module" does not exist type: mkdir C:\design\new_module, before changing directory.
Type the following: perl sv_mod_top.pl new_module_name.sv
When the script is finished you will see the message: "The script has finished successfully! You can now use new_module_name.sv."

How to use sv_inst.pl?

This utility is intended to make instantiation in SystemVerilog easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate.

	!! sv_inst.pl adder.sv

The script will retrieve the module definition from the file you specify and provide the instantiation for you in the current file at the cursor position.

For instance, if adder.sv contains the following definition:

        module adder (a, b, sum, carry);

                - or -

        module adder (input wire a, 
                      input wire b, 
                      output reg sum, 
                      output reg carry);

Then this is what the script will insert in your editor for you:

	adder adder (
		.a (a),
		.b (b),
		.sum (sum),
		.carry (carry) 
	        );

The keyword "module" must be left justified in the SystemVerilog file you are instantiating to work.

How to use sv_tb.pl?

This utility is intended to make creating new SystemVerilog HDL Test Bench modules easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate. This script will create a new text file called "tb_new_module_name.sv" when you type the following command:

        !! sv_tb.pl new_module_name.sv

The script will generate the SystemVerilog HDL test bench template for you with the port contents of "new_module_name.sv". Note: "new_module_name.sv" is the name of the existing SystemVerilog HDL file, and "tb_new_module_name.sv" is the new test bench file.

The script will retrieve the module definition from the "new_module_name.sv" file you specify and provide the instantiation for you in the new "tb_new_module_name.sv" file.

The keyword "module" must be left justified in the SystemVerilog file you are instantiating to work.

You can either use VI or a DOS Command prompt to run this script. If you want to use a DOS Command prompt, then see the instructions below:

Change directory to the desired directory
- cd C:\design\new_module
Type the following: perl sv_tb.pl new_module_name.sv
When the script is finished you will see the message: "The script has finished successfully! You can now use tb_new_module_name.sv."

Jeremy W. Webb

Senior Digital Hardware Engineer

Centellax, Inc.

3843 Brickway Blvd., Suite: 0100

Santa Rosa, CA 95403

Last Modified: Saturday, May 24, 2008 02:28:44 PM