Today is: Thursday March 18, 2010
This site contains information on my Master's Thesis Measurement Board design.
- Control FPGA ERS
Information on Peripheral devices, etc...
- Data Path FPGA ERS
Information on Measurement Board, Signal Processing, FPGA, etc... - Signal Source Data Path FPGA ERS
Information on Signal Source FPGA, etc...
PC Board:
- Schematics: meas_main_board.pdf - Black and White.
- Schematics: meas_main_board.pdf - Color.
- Assembly Top Diagram
- Assembly Bottom Diagram
- Bill of Materials - Excel Spreadsheet
- Bill of Materials - Text File
- Virtex-5 IODELAY Adjustments:
- ADC IODELAY Taps
- DAC IODELAY Taps
- DDR2 SDRAM IODELAY Taps
- QDR-II SRAM IODELAY Taps
- AsAPV2 No. 1 IODELAY Taps
- AsAPV2 No. 2 IODELAY Taps
- P342 PCB Top View Picture
- AsAPv2 PCB Location Top View Picture
- Measurement Board Turn-On Notes
Chassis:
Jeremy W. Webb Graduate Student Electrical and Computer Engineering Department One Shields Avenue Davis, CA 95616
Last Modified: Saturday, September 12, 2009 10:09:35 AM