Using Perl in your Verilog HDL Design Flow


Anyone who designs with Verilog HDL has probably grown tired of generating module instantiations in a hierarchical design, or creating a new top level or lower level Verilog HDL module. I have generated a few Perl Scripts that will automatically generate the module instantiations, top level module, and lower level module for you. These Perl Scripts can be invoked from within VI/VIM/GVIM, or a DOS Command Window. If you invoke them from within VI, the script output will be printed in the current file. If you invoke them from within a DOS Command Window, then you will have to either cut and paste into your Verilog HDL file or pipe the output to a new file. These files are hosted on GitHub at the link below:

Below are the scripts available in the GitHub VerilogTools project:

The scripts above have been modified to use a Perl Module named VerilogTools, which can be downloaded [here]. Simply unzip the file into a temporary directory, navigate to the directory named ./jwwebbopen-VerilogTools-*/module/ and execute the following commands:

                        [user@machine ../jwwebbopen-VerilogTools-v01/module/] 
                        $ perl Makefile.PL
                        [user@machine ../jwwebbopen-VerilogTools-v01/module/] 
                        $ make
                        [user@machine ../jwwebbopen-VerilogTools-v01/module/] 
                        $ sudo make install
                    

Follow VerilogTools on GitHub


How to use vertools.pl?


This utility is a combination of ver_mod_top.pl, ver_mod_low.pl, ver_inst.pl, ver_tb.pl, and ver_ucf.pl. This script implements the following functions:

                        Usage: vertools.pl [-h] [-v] [-i|-t|-u|-a|-z] [-f FILE]

                                -h              Print this help message.
                                -v              Verbose: Print Debug Information.
                                -i              Generate Verilog HDL Instantiation.
                                -t              Generate Verilog HDL Test Bench.
                                -u              Generate UCF file from Verilog HDL file.
                                -a              Generate new Verilog HDL top-level module file from Template.
                                -z              Generate new Verilog HDL low-level module file from Template.
                                -f FILE         Verilog HDL input file.

                                Example of Module Instantiation:
                                        vertools.pl -i -f sample.v
                    
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How to use ver_mod_top.pl?


This utility is intended to make creating new Verilog HDL modules easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate. This script will create a new text file called "top.v" when you type the following command:

                        !! ver_mod_top.pl -a -f top.v
                    

The script will generate the empty Verilog HDL template for you in the file "top.v". Note: "top.v" is the name of the new Verilog HDL file and can be anything you like. The module declaration uses Verilog 2001 ANSI-C style. You can either use VI or a DOS Command prompt to run this script. If you want to use a DOS Command prompt, then see the instructions below:

  1. Change directory to the desired directory; if necessary create a directory to store the new module.
  2.                             [user@machine ../fpga/src] 
                                $ mkdir top/
                                [user@machine ../fpga/src] 
                                $ cd top/
                                [user@machine ../fpga/src/top] 
                                $ 
                                
  3. Type the following: perl ver_mod_top.pl -a -f top.v
  4.                             [user@machine ../fpga/src/top] 
                                $ perl ver_mod_top.pl -a -f top.v
    
                                New Verilog HDL File: top.v is ready for use.
    
                                [user@machine ../fpga/src/top] 
                                $ 
                                
  5. When the script is finished you will see the message: "New Verilog HDL File: top.v is ready for use."
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How to use ver_mod_low.pl?


This utility is intended to make creating new Verilog HDL modules easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate. This script will create a new text file called "mymodule.v" when you type the following command:

                        !! ver_mod_low.pl -z -f mymodule.v
                    

The script will generate the empty Verilog HDL template for you in the file "mymodule.v". Note: "mymodule.v" is the name of the new Verilog HDL file and can be anything you like. The module declaration uses Verilog 2001 ANSI-C style. You can either use VI or a DOS Command prompt to run this script. If you want to use a DOS Command prompt, then see the instructions below:

  1. Change directory to the desired directory; if necessary create a directory to store the new module.
  2.                             [user@machine ../fpga/src] 
                                $ mkdir mymodule/
                                [user@machine ../fpga/src] 
                                $ cd mymodule/
                                [user@machine ../fpga/src/mymodule] 
                                $ 
                                
  3. Type the following: perl ver_mod_low.pl -a -f mymodule.v
  4.                             [user@machine ../fpga/src/mymodule] 
                                $ perl ver_mod_low.pl -a -f mymodule.v
    
                                New Verilog HDL File: mymodule.v is ready for use.
    
                                [user@machine ../fpga/src/mymodule] 
                                $ 
                                
  5. When the script is finished you will see the message: "New Verilog HDL File: mymodule.v is ready for use."
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How to use ver_inst.pl?


This utility is intended to make instantiation in Verilog HDL easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate.

                    	!! ver_inst.pl -i -f adder.v
                    

The script will retrieve the module definition from the file you specify and provide the instantiation for you in the current file at the cursor position.

For instance, if adder.v contains the following definition:

                            module adder (// ** Inputs **
                                          input wire a,         // Input A 
                                          input wire b,         // Input B

                                          // ** Outputs **
                                          output reg sum,       // Output Sum
                                          output reg carry      // Output Carry
                                         );
                    

Then this is what the script will insert in your editor for you:

                    	adder adder (.a (a),
                            		 .b (b),
                            		 .sum (sum),
                            		 .carry (carry));
                    

The keyword "module" must be left justified in the Verilog HDL file you are instantiating to work.

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How to use ver_tb.pl?


This utility is intended to make creating new Verilog HDL Test Bench modules easier. This script will create two new text files called "test_mymodule.v" and "top.v" when you type the following command:

                            !! ver_tb.pl -t -f mymodule.v
                    

The script will generate the Verilog HDL test bench template for you with the port contents of "mymodule.v". Note: "mymodule.v" is the name of the existing Verilog HDL file, "test_mymodule.v" is the new test bench file, and "top.v" is the top level of the simulation test bench that instantiates the module or unit under test and the stimulus.

The script will retrieve the module definition from the "mymodule.v" file you specify and provide the instantiation for you in the new "top.v" file along with the instantiation for the stimulus "test_mymodule.v".

The keyword "module" must be left justified in the Verilog HDL file you are instantiating to work.

You can either use either a bash terminal or a DOS Command prompt to run this script. Instructions are provided below:

  1. Change directory to the desired directory.
  2.                             [user@machine ../fpga/src] 
                                $ cd mymodule/
                                [user@machine ../fpga/src/mymodule] 
                                $ 
                                
  3. Type the following: perl ver_tb.pl -t -f mymodule.v
  4.                             [user@machine ../fpga/src/mymodule] 
                                $ perl ver_tb.pl -t -f mymodule.v
    
                                Test Bench File(s): test_mymodule.v and top.v are ready for use.
    
                                [user@machine ../fpga/src/mymodule] 
                                $ 
                                
  5. When the script is finished you will see the message: "Test Bench File(s): test_mymodule.v and top.v are ready for use."
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How to use ver_ucf.pl?


This utility is intended to make the creation of UCF files for Xilinx designs easier.

As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to generate a UCF from.

                    	!! ver_ucf -u -f adder.v
                    

The script will retrieve the input/inout/output definitions from the file you specify and reformat it into the UCF format. It will then write a new file called "adder.ucf", which contains the pin assignments. Below is an example of the UCF file contents:

                                                                              
                        #*****************************************************************
                        #
                        # adder.ucf module
                        #
                        #*****************************************************************
                        #
                        # My Company Confidential Copyright  2017 Research Department
                        #
                        #*****************************************************************
                        #
                        # created on:	05/02/2017
                        # created by:	Jeremy W. Webb
                        # last edit on:	05/02/2017
                        # last edit by:	Jeremy W. Webb
                        # revision:	001
                        # comments:	Generated.
                        #
                        # board name:		My Board
                        # board number:		xxx
                        # board revision:	A
                        # device mpn:		XC3Sxxx-4VQ100C
                        # 
                        #******************************************************************
                        #
                        #--------------------------------------
                        # T I M I N G   C O N S T R A I N T S
                        #--------------------------------------
                        # N/A

                        #--------------------------------------
                        # P I N   A S S I G N M E N T S 
                        #--------------------------------------
                        NET "FPGA_10MHz" LOC = "" | IOSTANDARD = LVCMOS33;
                        NET "FPGA_INT_SWP" LOC = "" | IOSTANDARD = LVCMOS33;
                        NET "FPGA_ID"  LOC = "" | IOSTANDARD = LVCMOS33;                          
                    

The pin numbers are left blank for you to fill in with the correct values.

You can either use a bash terminal or a DOS Command prompt to run this script. Instructions are provided below:

  1. Change directory to the desired directory.
  2.                             [user@machine ../fpga/src] 
                                $ cd adder/
                                [user@machine ../fpga/src/adder] 
                                $ 
                                
  3. Type the following: perl ver_ucf.pl -u -f adder.v
  4.                             [user@machine ../fpga/src/adder] 
                                $ perl ver_ucf.pl -u -f adder.v
    
                                UCF File: adder.ucf is ready for use.
    
                                [user@machine ../fpga/src/adder] 
                                $ 
                                
  5. When the script is finished you will see the message: "UCF File: adder.ucf is ready for use."
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