Anyone who designs with VHDL has probably grown tired of generating components or module instantiations in a hierarchical design. With the help of Tom Anderson, I was able to generate a couple of Perl Scripts that will automatically generate the component and module instantiations for you. These Perl Scripts can be invoked from within VI/VIM/GVIM, or a DOS Command Window. If you invoke them from within VI, the script output will be printed in the current file. If you invoke them from within a DOS Command Window, then you will have to cut and paste into your VHDL file. These files are hosted on GitHub at the link below:
Below are the scripts available in the GitHub VHDLTools project:
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This utility is intended to make instantiation in VHDL easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate.
!! vhdl_inst adder.vhd
The script will retrieve the module definition from the file you specify and provide the instantiation for you in the
current file at the cursor position.
For instance, if adder.vhd contains the following definition:
entity adder is
port (
a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end adder;
Then this is what the script will insert in your editor for you:
adder : adder
port map (
a => a,
b => b,
sum => sum,
carry => carry
);
The keyword "entity" must be left justified in the vhdl file you are instantiating to work.
Back to TopThis utility is intended to make instantiation in VHDL easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate.
!! vhdl_comp adder.vhd
The script will retrieve the module definition from the file you specify and provide the instantiation for you in the
current file at the cursor position.
For instance, if adder.vhd contains the following definition:
entity adder is
port (
a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end adder;
Then this is what the script will insert in your editor for you:
component adder
port (
a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end component;
The keyword "entity" must be left justified in the vhdl file you are instantiating to work.
Back to TopThis utility is intended to make creating new VHDL modules easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate. This script will create a new text file called "new_module_name.vhd" when you type the following command:
!! vhdl_mod.pl new_module_name.vhd
The script will generate the empty VHDL template for you in the file "new_module_name.vhd". Note: "new_module_name.vhd" is the name of the new VHDL file and can be anything you like. You can either use VI or a DOS Command prompt to run this script. If you want to use a DOS Command prompt, then see the instructions below:
This utility is intended to make creating new VHDL modules easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate. This script will create a new text file called "new_module_name_tb.vhd" when you type the following command:
!! vhdl_tb.pl new_module_name.vhd
The script will generate the VHDL test bench template for you with the port
contents of "new_module_name.vhd". Note: "new_module_name.vhd" is the name
of the existing VHDL file, and "new_module_name_tb.vhd" is the new test bench
file.
The script will retrieve the module definition from the "new_module_name.vhd"
file you specify and provide the instantiation for you in the new
"new_module_name_tb.vhd" file.
The keyword "entity" must be left justified in the vhdl file you are
instantiating to work.
You can either use VI or a DOS Command prompt to run this script. If you want to
use a DOS Command prompt, then see the instructions below: